1. Field of the Invention
The present invention relates to a thin film transistor (TFT), a method of fabricating the same, and a display device including the TFT, and more particularly, to a TFT in which a channel region is connected to a gate electrode, and a method of fabricating the same.
2. Description of Related Art
An organic light emitting diode (OLED) display device is an emissive device with excellent viewing angle and contrast. Since a separate light source such as a backlight is not required, unlike liquid crystal display devices (LCDs), the OLED display device may be made lightweight and thin, and consumes less power than conventional cathode ray tube (CRT) display devices.
Furthermore, the OLED display device can be driven with direct current at a low voltage and has a fast response speed. Also, since the OLED display device is fabricated using only solid materials, it is highly resistant to external shock, can be used in an environment having a wide range of temperatures, and is simple and inexpensive to manufacture.
Some flat panel displays (FPDs), such as an OLED display device or an LCD, employ thin film transistors (TFTs) as switching devices and/or driving devices.
The TFTs used in these FPDs, may be bottom-gate TFTs.
FIG. 1 is a cross-sectional view of a conventional bottom-gate TFT.
Referring to FIG. 1, a buffer layer 101 is disposed on a substrate 100, such as a glass substrate or a plastic substrate, a gate electrode 102 is disposed on the buffer layer 101, a gate insulating layer 103 is disposed on the entire surface of the substrate 100 on which the gate electrode 102 is disposed, and a semiconductor layer 104 is disposed on the gate insulating layer 103 at a position corresponding to the gate electrode 102.
The semiconductor layer 104 includes at least a channel region 104a and source and drain regions 104b. Also, source and drain electrodes 105 are respectively disposed on the source and drain regions 104b of the semiconductor layer 104, and electrically connected to the source and drain regions 104b, respectively. In this case, a heavily doped silicon layer, i.e., an n+ silicon layer 106 is disposed on the source and drain regions 104b in order to lower contact resistance between the source and drain regions 104b and the source and drain electrodes 105, respectively.
However, when the bottom-gate TFT is used in an FPD such as an OLED display device, a substrate bias leads to an increase in a threshold voltage, and a subthreshold slope deteriorates.